august 2009 copyright ? alliance memory inc. . all rights reserved. ? as7c1025b 5v 128k x 8 cmos sram (center power and ground) aug 2009 v 1.4 alliance memory inc. p. 1 of 9 features ? industrial and comm ercial temperatures ? organization: 131,072 x 8 bits ? high speed - 1 0/12/15/20 ns addres s access time - 5/6/7/8 ns output enable access time ? low power consumption: active - 605mw / max @ 10 ns ? low power consumption: standby - 55 mw / max cmos ? 6 t 0.18 u cmos technology ? easy memory expansion with ce , oe inputs ? center power and ground ? ttl/lvttl-compatible , three-state i/o ? jed ec-s tandard packages - 32-pin, 300 mil soj - 32-pin, 400 mil soj ? esd protection 2000 volts ? l atch-up current 200 ma logic block diagram 512 x 256 x 8 array (1, 048, 57 6) se nse amp in pu t bu ffer a10 a11 a12 a13 a14 a15 a16 i/o0 i/o7 oe ce we colu mn decoder row de cod er control circuit a9 a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a16 a15 a14 a13 oe i/o7 i/o6 gnd v cc i/o5 i/o4 a12 a11 a10 a9 a8 a0 a1 a2 a3 ce i /o0 i /o1 v cc gnd i /o2 i /o3 we a4 a5 a6 a7 as7c1025b 32-pin soj (300 mil) 32-pin soj (400 mil) selection guide -10 -12 -15 -20 unit m aximum address ac ce ss time 10 12 15 20 ns m aximum output enable access tim e 5 6 7 8 ns maximum operating current 110 100 90 80 ma maximum cm os standby current 10 10 10 10 ma
as7c1025b aug/09 , v. 1.4 alliance memory inc. p. 2 of 9 ? functional description the as7c1025b is a high-performance cmos 1,048,576-bit static ra ndom access memory (sram) de vices organized as 131,072 x 8 bits. they are designed for memory applic ations where fast data access, low pow er, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with output enable access times (t oe ) of 5/6/7/8 ns are ideal for high- performance applications. the chip enable input ce permits easy memory and expansion with multiple-bank memory systems. when ce is high, the device enters standby mode. if input s are still toggling, the device will consume i sb power. if the bus is static, then full standby power is reached (i sb1 ). for example, the as7c1026b is guaranteed not to exceed 55 mw under nominal full standby conditions. a write cycle is accomplished by asserting write enable ( we ) and chip enable ( ce ). data on the input pins i/o0 through i/o7 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable ( oe ) or write enable ( we ). a read cycle is accomplished by asserting output enable ( oe ) and chip enable ( ce ), with write enable ( we ) high. the chips drive i/o pins with the data word referenced by the input address. when either chip enable or output enable is inactive or write enable is act ive, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl-compat ible, and operation is from a single 5 v suppl y. the as7c1025b is packaged in common industry standard packages. note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these or any other conditions ou tside those indicated in the operational sections of this spe cification is not implied. exposure to absolute maximum rating conditions for extended peri ods may affect reliability. key: x = don?t care, l = low, h = high. absolute maximum ratings parameter symbol min max unit voltage on v cc relative to gnd v t1 ?0.50 +7.0 v voltage on any pin relative to gnd v t2 ?0.50 v cc + 0.5 v power dissipation p d ?1 . 0w storage temperature (plastic) t stg ?65 +150 o c ambient temperature with v cc applied t bias ?55 +125 o c dc current into outputs (low) i out ?2 0m a truth table ce we oe data mode h x x high z standby (i sb , i sb1 ) l h h high z output disable (i cc ) lhl d out read (i cc ) llx d in write (i cc )
as7c1025b aug/09 , v. 1.4 alliance memory inc. p. 3 of 9 ? v il min = -1.0v for pulse width less than 5ns v ih max = v cc +2.0v for pulse width less than 5ns. recommended operating conditions parameter symbol min nominal max unit supply voltage v cc 4.5 5.0 5.5 v input voltage v ih 2.2 ? v cc + 0.5 v v il ?0.5 ? 0.8 v ambient operating temperature commercial t a 0? 70 o c industrial t a ?40 ? 85 o c dc operating characteristics (over the operating range) 1 parameter symbol test conditions -10 -12 -15 -20 unit min max min max min max min max input leakage current | i li | v cc = max, v in = gnd to v cc ?1?1?1?1 a output leakage current | i lo | v cc = max, ce = v ih , v out = gnd to v cc ?1?1?1?1 a operating power supply current i cc v cc = max ce v il , f = f max, i out = 0 ma ? 110 ? 100 ? 90 ? 80 ma standby power supply current 1 i sb v cc = max ce v ih , f = f max ?50?45?45?40ma i sb1 v cc = max ce v cc ?0.2 v, v in 0.2 v or v in v cc ?0.2 v, f = 0 ? 10 10 10 10 ma output voltage v ol i ol = 8 ma, v cc = min ? 0.4 ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 2.4 ? 2.4 ? 2.4 ? v capacitance ( f = 1 mhz, t a = 25 o c, v cc = nominal ) 2 parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe v in = 0 v 5 pf i/o capacitance c i/o i/o v in = v out = 0 v 7 pf
as7c1025b aug/09 , v. 1.4 alliance memory inc. p. 4 of 9 ? key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read waveform 2 (ce and oe controlled) 3,6,8,9 read cycle (over the operating range) 3,9 parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max read cycle time t rc 10 - 12 ? 15 ? 20 ? ns address access time t aa - 10 ? 12 ? 15 ? 20 ns 3 chip enable ( ce ) access time t ace - 10 ? 12 ? 15 ? 20 ns 3 output enable ( oe ) access time t oe -5?6?7?8 ns output hold from address change t oh 3 - 3 ? 3 ? 3 ? ns 5 ce low t o output in low z t clz 3 - 3 ? 3 ? 3 ? ns 4, 5 ce low to output in high z t chz - 4 ? 5 ? 6 ? 7 ns 4, 5 oe low to output in low z t olz 0 - 0 ? 0 ? 0 ? ns 4, 5 oe high to output in high z t ohz - 4 ? 5 ? 6 ? 7 ns 4, 5 power up time t pu 0 - 0 ? 0 ? 0 ? ns 4, 5 power down time t pd - 10 ? 12 ? 15 ? 20 ns 4, 5 undefined/don?t care falling input rising input a ddress d out data valid t oh t aa t rc current supply oe d out t oe t olz t ace t chz t clz t pu t pd i cc i sb 50% 50% data valid t rc1 ce t ohz
as7c1025b aug/09 , v. 1.4 alliance memory inc. p. 5 of 9 ? write waveform 1 (we controlled) 10,11 write cycle (over the operating range) 11 parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max write cycle time t wc 10 - 12 ? 15 ? 20 ? ns chip enable ( ce ) to write end t cw 8-9?10?12? ns address setup to write end t aw 8-9?10?10? ns address setup time t as 0-0?0?0? ns write pulse width t wp 7 - 8 ? 9 ? 12 ? ns write recovery time t wr 0-0?0?0? ns address hold from end of write t ah 0-0?0?0? ns data valid to write end t dw 5 - 6 ? 8 ? 10 ? ns data hold time t dh 0 - 0 ? 0 ? 0 ? ns 4, 5 write enable to output in high z t wz - 5 ? 6 ? 7 ? 8 ns 4, 5 output active from write end t ow 1 - 1 ? 1 ? 2 ? ns 4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t wr
as7c1025b aug/09 , v. 1.4 alliance memory inc. p. 6 of 9 ? write waveform 2 (ce controlled) 10,11 ac test conditions notes 1 during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a and b. 4t clz and t chz are specified with cl = 5 pf, as in figure b. transition is measured 500 mv from steady-state voltage. 5 this parameter is guaran teed, but not 100% tested. 6 we is high for read cycle. 7 ce and oe are low for read cycle. 8 address is valid prior to or coincident with ce transition low. 9 all read cycle timings are referen ced from the last valid address to the first transitioning address. 10 n/a 11 all write cycle timings are referenced from the la st valid address to the first transitioning address. 12 n/a. 13 c = 30 pf, except all high z and low z parameters where c = 5 pf. t aw address ce we d out t cw t wp t dw t dh t ah t wz t wc t as data valid d in t wr ? output load: see figure b. ? input pulse level: gnd to 3.5 v. see figure a. ? input rise and fall times: 2 ns. see figure a. ? input and output timing reference levels: 1.5 v. 168 ? ? ?
as7c1025b aug/09 , v. 1.4 alliance memory inc. p. 7 of 9 ? package dimensions e d e1 pin 1 b b a1 a2 c e seating plane e2 a 32-pin soj 300 mil/400 mil symbol 32-pin soj 300 mil 32-pin soj 400 mil min max min max a 0.128 0.145 0.132 0.146 a1 0.025 - 0.025 - a2 0.095 0.105 0.105 0.115 b 0.026 0.032 0.026 0.032 b 0.016 0.020 0.015 0.020 c 0.007 0.010 0.007 0.013 d 0.820 0.830 0.820 0.830 e 0.255 0.275 0.354 0.378 e1 0.295 0.305 0.395 0.405 e2 0.330 0.340 0.435 0.445 e 0.050 bsc 0.050 bsc
as7c1025b aug/09 , v. 1.4 alliance memory inc. p. 8 of 9 ? note: add suffix ?n? to the above part nu mber for lead free parts. (ex as7c1025b-10tjcn) ordering codes package \ access time temperature 10 ns 12 ns 15 ns 20 ns 300-mil soj commercial as7c1025b-10tjc as 7c1025b-12tjc as7c1025b-15tjc as7c1025b-20tjc industrial AS7C1025B-10TJI as7c1025b-1 2tji as7c1025b-15tji as7c1025b-20tji 400-mil soj commercial as7c1025b-10jc as7 c1025b-12jc as7c1025b-15jc as7c1025b-20jc industrial as7c1025b-10ji as7c1025b-12ji as7c1025b-15ji as7c1025b-20ji part numbering system as7c 1025b ?xx x x x sram prefix device number access time package: tj = soj 300 mil j = soj 400 mil temperature range c = commercial, 0 c to 70 c i = industrial, -40 c to 85 c n = lead free part
? as7c1025b ? alliance memory, inc. 511 taylor way, san carlos , ca 94 070 tel: 650- 610-6800 fax: 650- 620-9211 www.alliancememory.com copyright ? alliance memory all rights reserved part number: a s7c1025b document version: v. 1.4 ? copyright 200 9 allia nce memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or re gistered trademarks of allianc e. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are pos sible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or customer. alliance do es not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warra nties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, e xcept as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and conditions of sale. the purchase of products from allia nce does not convey a license under any patent rights, copyrig hts; mask works rights, trademarks, or any other intellectual property rights of allianc e or third parties. alliance do es not authorize its products fo r use as critical components in life-supporting systems where a malfunction or failure may reasonabl y be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to inde mnify alliance against all claims arising from such use.
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